1. Field of the Invention
This invention generally relates to a semiconductor device, and more particularly to a silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection.
2. Description of Related Art
ESD occurs due to the movement of electrostatic charges on a non-conductor, which causes the damage of the semiconductor devices and other circuits in the IC. For example, when the relative humidity is higher, several hundred or thousand Volts of electrostatic voltage will be detected on a human body walking on the carpet. When the relative humidity is lower, more than ten thousand Volts of electrostatic voltage will be detected on a human body. Likewise, several hundred or thousand Volts of electrostatic voltage will be detected on an equipment for packing or testing the IC due to the humidity or other factors. When the subjects with electrostatic charges contact the chips, the subjects will discharge the electrostatic charges toward the chips. The instant discharging power may seriously damage the circuits in the chips.
Therefore, to prevent the ESD from damaging the circuits in the chips, several ESD protection devices are proposed. FIG. 1 is a block diagram of a traditional ESD protection device. Referring to FIG. 1, the prior art provides an ESD protection circuit 102 on the I/O pad 100 of the chip as the discharging path to prevent the circuit from being damaged. In a normal condition, the circuit in FIG. 1 works as if the ESD protection circuit 102 does not exist so that the I/O pad is directly coupled to the internal circuit 104. When a high voltage pulse (i.e., the voltage generated due to electrostatic discharge) occurs, the ESD protection circuit 102 can prevent the current from I/O pad from entering into the internal circuit 104 in order to protect the internal circuit 104.
In the prior art, the metal oxide semiconductor (MOS) transistor is used as the ESD protection device. FIG. 2 is a cross-sectional view of a high voltage NMOS (HVNMOS) transistor. FIG. 3 is an ideal voltage-current characteristic curve of a HVNMOS transistor. Referring to FIGS. 2 and 3, when the drain 202 is applied with an increasing ESD voltage, the current of the HVNMOS transistor will slowly increase as the increasing ESD voltage. When the ESD voltage reaches the triggering voltage Vt1, the junction of the P substrate 200 and the N-deep well will break down. In the meantime, the current increases rapidly and the voltage decreases as the current increases. When the voltage of the HVNMOS reaches the holding voltage Vh, even if the current increases quickly, the voltage maintains at the same level (or increases very slowly).
However, when the voltage applied to a typical HVNMOS transistor is higher than the triggering voltage Vt1, the reverse-biased drain-substrate junction goes into avalanche breakdown, because the largest tolerable forward current It2 of the HVNMOS transistor can tolerate is too small, the second junction breakdown would occur in a very short time. The HVNMOS transistor thereby cannot snap back and fails immediately to generate leakage current. Consequently, the HVNMOS transistor becomes ineffective. In light of the above, the HVNMOS transistor alone cannot be the ESD protection device.
To provide the HVNMOS transistor with the ESD protection device, an embedded SCR is formed in the HVNMOS transistor to increase the largest tolerable ESD current of the HVNMOS transistor according to the prior art. As a result, the tolerance of the HVNMOS transistor to the ESD is enhanced. FIG. 4 shows the cross-sectional view of the HVNMOS transistor with an embedded SCR and the equivalent circuit thereof. Referring to FIG. 4, the P-doped region 410 and N-doped region 408 constitute the drain 404. The P-doped region 410, the N deep well 402, and the P substrate 400 form a PNP BJT 414; the N deep well 402, the P substrate 400, and the source 406 form a NPN BJT 412.
The collectors of the PNP BJT and the NPN BJT are coupled to the bases of the other BJTs to form a P-N-P-N semiconductor device with three junctions. This parasitic device with the P-N-P-N junction is so-called embedded SCR, which can enhance the tolerance of the transistor to the ESD.